Manipulating stress is an effective way of improving the minority carrier mobility in a metal oxide semiconductor field effect transistor (MOSFET) and increasing the transconductance (or reduced serial resistance) of the MOSFET that requires relatively small modifications to semiconductor processing while providing significant enhancement to MOSFET performance.
When stress is applied to the channel of a semiconductor transistor, the mobility of carriers, and as a consequence, the transconductance and the on-current of the transistor, are altered from their original values for an unstressed semiconductor. This is because the applied stress and the resulting strain on the semiconductor structure within the channel affects the band gap structure (i.e., breaks the degeneracy of the band structure) and changes the effective mass of the carriers. The effect of the stress depends on the crystallographic orientation of the plane of the channel, the direction of the channel within the crystallographic orientation, and the direction of the applied stress.
The effect of uniaxial stress, i.e., a stress applied along one crystallographic orientation, on the performance of semiconductor devices, especially on the performance of a MOSFET (or a “FET” in short) device built on a silicon substrate, has been extensively studied in the semiconductor industry. For a PMOSFET (or a “PFET” in short) utilizing a silicon channel, the mobility of minority carriers in the channel (which are holes in this case) increases under uniaxial compressive stress along the direction of the channel, i.e., the direction of the movement of holes or the direction connecting the drain to the source. Conversely, for an NMOSFET (or an “NFET” in short) devices utilizing a silicon channel, the mobility of minority carriers in the channel (which are electrons in this case) increases under uniaxial tensile stress along the direction of the channel, i.e., the direction of the movement of electrons or the direction connecting the drain to the source. These opposite requirements for the type of stress for enhancing carrier mobility between the PMOSFETs and NMOSFETs have led to prior art methods for applying at least two different types of stress to the semiconductor devices on the same integrated chip.
Different methods of “stress engineering,” or “strain engineering” as it is alternatively called, on the channel of a MOSFET have been known in the prior art.
One group of methods create a “global stress,” that is, a stress applied to a general transistor device region generated from the substrate. A global stress is generated by such structures as SiGe stress relaxed buffer layers, Si:C stress relaxed buffer layers, or silicon germanium structures on an insulator.
Another group of methods generate a “local stress,” that is, a stress applied only to local areas adjacent to the channel from a local structure. A local stress is generated by such structures as stress liners, embedded SiGe source/drain structures, embedded Si:C source/drain structures, stress-generating shallow trench isolation structures, and stress-generating silicides. An increase in the on-current of up to 50% and an overall chip speed increase up to 40% have been reported on semiconductor devices utilizing these methods.
A method of applying a local stress is a technique that is commonly referred to as “stress memorization technique,” according to which a tensile stress generating dielectric film is deposited over a structure, e.g., a field effect transistor, to which tensile stress is to be applied. During a high temperature anneal, the tensile stress generating film applies tensile stress to the underlying semiconductor devices. After the anneal, the stress applied to the underlying semiconductor devices is frozen, or “memorized,” hence the name “stress memorization technique.” After the tensile stress generating dielectric film is removed, the underlying structure still maintains the memorized stress. Use of a highly tensile nitride film as a stress generating film has been successfully demonstrated, resulting in a uniaxial tensile stress on the order of about 2 GPa along the direction of the channel of an NFET.
Generation of a compressive stress through a stress memorization technique, i.e., application of a compressive stress on a semiconductor device by transferring compressive stress from a compressive stress generating liner, has proven to be difficult since compressive nitride films tend to relax during a high temperature anneal, resulting in a stress transfer of only an insignificant level of stress, e.g., a compress stress on the order of, or less than, 100 MPa in magnitude.
Further, known stress memorization techniques generate a stress on the order of, or less than, about 3 GPa. Since the alteration of the band structure is proportional to the magnitude of the stress, an even higher level of uniaxial stress is expected to enhance the mobility of one of the two types of MOSFETs, i.e., one of the PFETs and NFETs.
In view of the above, there exists a need for a compressive stress memorization technique that transfers compressive stress to a semiconductor device, e.g., a PFET.
Also, there exists a need for a semiconductor structure and methods of manufacturing the same wherein both p-type and n-type semiconductor devices have enhanced minority carrier mobility by employing a dual stress memorization technique, that is, a compressive stress memorization technique on one type of devices and a tensile stress memorization technique on another type of devices.
Furthermore, there exists a need for a structure and methods of manufacturing the same wherein a higher level of stress is transmitted to at least one of the two types of field effect transistors, i.e., PFETs and NFETs.